LONDON — Inapac Technology Inc., a system-in-package (SiP) memory integrator, has announced two components, a 32-Mbit SDRAM and a 64-Mbit DDR SDRAM. The 64-Mbit DDR design features 32-bit interface to provide superior graphics and video performance in consumer applications, the company said.
Individual memory die are made using a 0.14-micron process and the designs and full test methodology support are available for licensing and production ramp, Inapac (San Jose, Calif.) said. The two memories are part of Inapac’s SiPFLOW production flow, which includes a family of memory IP designs, a testing infrastructure, and SiP testing services and support.
Inapac appears to be changing its business model. Originally described as a fabless DRAM company the company now seems prepared to license designs it creates together with burn-in and ATE technology to other fabless memory integrators or OEMs.
The company did not disclose the name of its DRAM foundry. However, Taiwan DRAM maker ProMos Technologies Inc. contributed to a $15 million third round of financing June 2004.
“Experience with our first design, a 16-Mbit SDRAM that has already been implemented in high-volume production, has shown that the SiPFLOW platform can deliver exceptional, less-than-200 dppm reliability at low cost,” said Naresh Baliga, vice president of marketing for Inapac Technology. “With this proven methodology, we're expanding the range of our licensable designs to offer the density and speed grades needed to meet a broader range of SiP design requirements.”
The 32M-bit designs, operate at up to 200-MHz clock frequency and a t voltages of 3.3-V, 2.5-V, or 1.8-V. The 64M-bit designs, available in 250-MHz at 2.5-V or 133-MHz at 1.8-V versions, are sampling now, Inapac said.