SAN FRANCISCO — Aldec Inc. has released a new version of its Active-HDL 7.1 FPGA and ASIC design entry and verification platform, including several new tools.
Aldec (Henderson, Nev.) said new tools found in the release include ultra-high speed gate-level simulation technology (SLP), VHDL and Verilog linting tools, improved support for Matlab and Simulink and new SystemVerilog simulation support.
According to Aldec, the SLP simulation acceleration technology employs a completely re-designed simulation engine that dramatically reduces simulation run times for Verilog gate-level and timing verification. SLP is transparent to the user, is easy to employ and also reduces simulation run times for VHDL designs, most notably in timing simulations, Aldec said.
Aldec said Active-HDL Design Flow Manager was updated to support the latest synthesis, place and route, and other vendor tools.
Active-HDL 7.1 is currently available. Pricing information was not disclosed. A free evaluation copy is available on Aldec's Web site (http://www.aldec.com/products/active-hdl).
