[ Technology Blogs Articles News Reviews ]

 
Google
www Technoclicks.com
Post Tech Blog Article News Reviews

Top Articles

RISC core adds muscle to Renesas microcontroller

Posted by inet - 2006-04-16

SAN JOSE — A Renesas microcontroller employs proprietary flash memory and circuit technologies and an enhanced 32-bit SH-2 RISC core architecture that can simultaneously execute two instructions per cycle. Designated the SH7211F, the microcontroller can deliver a 1.5X performance improvement compared to previous microcontrollers.

According to Renesas, the microcontroller’s performance is improved by 3X when the 80 MHz maximum operating frequency of SH-2 devices is considered.

"Able to operate at clock rates of up to 160 MHz, the SH7211F delivers a throughput of close to 320 MIPS, thus allowing embedded systems to deliver more precise and faster control functions and faster software execution,” said Peter Carbone, marketing director, System LSI business unit at Renesas Technology America.

To accommodate complex and sophisticated application programs, the microcontroller includes a large amount of flash storage and on-chip SRAM-- 512 kbytes and 32 kbytes, respectively. In general, though, the operating speed of flash memory is typically slower than that of the logic circuitry in the CPU core, and the flash speed is difficult to increase. However, the SH7211F incorporates proprietary Renesas flash memory technology and leverages novel circuit techniques to implement a flash-memory cache structure, explained Carbone.

These factors combine to allow the SH7211F to produce virtually the same performance as when single-cycle accesses are performed at 160 MHz. Also, because the SH-2A CPU core improves ROM code efficiency, program size can be reduced by about 25 percent compared with code written for chips that have the SH-2 core. A 32-bit multiplier also helps accelerate signal processing and other algorithms.

The enhanced SH-2A core incorporates 15 register banks specifically for interrupt use. The response time for handling an interrupt is only 6 cycles, compared to 37 cycles for the SH-2 core. This enhancement, coupled with the core's 160 MHz operating frequency, cuts the program interrupt response time to approximately 1/12 of that of an SH-2 core operating at 80 MHz. This ensures fast program switching when an interrupt event occurs, thus improving real-time control.

The SH7211 also includes two multifunction timer units with 3-phase pulse width modulation (PWM) output capability to control AC servos or two motors simultaneously. An 8-channel, 12-bit A/D converter and a 2-channel 8-bit D/A converter and various communication functions reside on chip. A bus-state controller enables flash ROM, SRAM, SDRAM, burst ROM, multiplex I/O, and others devices to connect directly to the microcontroller's external data bus.

Development environments include a USB bus-powered E10A-USB emulator, and the more capable E200F emulator that allows real-time tracing at the microcontrollers's maximum operating frequency.

Available in sample quantities, the SH7211F comes housed in a 144-lead LQFP and sells for $19.84 apiece.



Related Category :

Network ||

Next ....: Cisco Partner Helps Town Deploy Wireless Mesh Solution For Boston Marathon

:: Previous Articles
:: Intel invests in silver-zinc battery developer
:: Exabyte Shipping Low-cost Tape Automation For SMBs
:: Cisco Provides Consolidation Options For the Enterprise

Recent Articles

 


 

Home | | Members | Search | Upadtes | RSS | Tags | Site Map | Tags | Conact

© Technoclicks.com - All rights reserved.