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IEEE standardizes 'e' verification language

Posted by iNext - 2006-04-05

SANTA CRUZ, Calif. — The "e" hardware verification language developed by Verisity Inc. has been ratified as the IEEE 1647 standard, EE Times has learned. The ratification may pave the way for broader acceptance of the language, which faces a challenge from SystemVerilog, also now an IEEE standard.

A brief statement on the IEEE 1647 web site notes that the standard was officially approved by the IEEE as of March 30. Earlier in the week, the IEEE RevCom committee recommended approval of the standard, which was subsequently ratified by the IEEE Standards Activity Board.

The approval was expected, given that the IEEE sponsor ballot for standardization of "e" passed overwhelmingly in November 2005. Cadence Design Systems, which acquired Verisity last year, was a strong supporter of the standardization effort, and it contributed resources for technical editing and program management.

The "e" language is used in Cadence's Specman testbench development product. Some observers, however, believe that SystemVerilog may make "e" obsolete, a view voiced by many verification engineers in a survey conducted last year by John Cooley.

But advocates of "e" disagree, saying that the language supports verification at a higher level of abstraction than SystemVerilog. Last year Verisity veteran Steve Glaser, now vice president of marketing for Cadence's verification division, cited 15,000 Specman licenses, more than 300 corporate customers, an estimated 50 million lines of "e" code and over 500 verification intellectual-property (VIP) components.

"We fully expect large EDA vendors to support 'e' sometime in the future," Glaser said at the time. "We expect, because there's real business demand, that many e-based tools will emerge from this [IEEE] standard."

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