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Hitachi advances paper-thin RFID chip

Posted by iTech - 2006-02-07

TOKYO — Hitachi Ltd. has developed a 0.15 millimeter by 0.15 millimeter, 7.5 micron thick IC for radio-frequency identification applications, which the company claimed is the smallest and thinnest in the world.

Hitachi was due to present details of the chip on Sunday (Feb. 5) at the IEEE International Solid-State Circuits Conference (ISSCC 2006), being held Feb. 5 to Feb. 9 in San Francisco, California.

Paper is typically 80 microns to 100 microns thick and the chip substrate has been made small and thinned to 7.5 micron to ease application in paper where it could be used an intelligent watermark.

Hitachi has been pursuing such “embedded” applications for its “mu-chip” for a number of years. The company integrated an antenna on an earlier version of the chip in September 2003. Hitachi has reduced the plan dimensions and the thickness of the chip in the latest version.

"The smallness is one [important] function for RF IC chip," said Mitsuo Usami, senior chief researcher of Hitachi's Central Research Laboratory, who invented Hitachi's mu-chip initiative. “We fabricated the prototype using technology widely used for volume production," he said.

This time around the R&D team used silicon on insulator (SOI) technology to create a yet smaller version of chip. "When I presented a 0.3 millimeter by 0.3 millimeter chip at ISSCC in 2003, I was thinking about the use of SOI wafers as the next step," said Usami. The 0.3-mm by 0.3-mm chip was 60 micron thick. Using an SOI wafer, which has a thin silicon layer on top of an insulator layer, the Hitachi team fabricated the 4-metal layer CMOS on the SOI wafer and etched from backside to remove the silicon substrate. Etching stops at the insulator layer, leaving the 7.5-micron thick chip. If a chip were to be made thin by grinding a wafer from the backside, precise control would be required and would be impossible to grind a wafer precisely 7.5 micron thick, according to Usami. Even though the chip is thinner because of its smaller size it has increased robustness, he said.

In conventional mu-chip design a doped guard ring structure was necessary to separate high frequency elements in the RF IC chip and to prevent interference, but the elements on the SOI wafer can be separated in dedicated wells bounded at the bottom and on the sides by silicon dioxide, which allowed further size reduction.

"I believe that mu-chip is about two generation in advance of other prototypes," said Usami. Hitachi started offering a 0.4-mm by 0.4-mm “mu-chip” in October 2001. It receives 2.45-GHz microwaves with an external antenna for applications in Japan and transmits back a 128-bit ID number. The ID is written into the chip's read only memory during fabrication. The newly developed 0.15-mm by 0.15-mm chip has the same function and has been shown to work.

Hitachi's first mu-chip was used for the admission ticket for the 2005 World Exposition, Aichi, Japan, held six months from March last year. Compared to that chip the latest version is nearly one fifteenth the size. The prototype used a 180-nm process, but when it goes to volume production, the process will shrink along with the industry's roadmap, Usami said.

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