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Stacked SRAM cells support programmable startup

Posted by iMark - 2005-12-25

LONDON — Viciciv Technologies Inc. is a startup company that appears to be preparing to enter the FPGA or programmable ASIC market, using patented stacked SRAM cell technology.

The company has been assigned a patent that appears to cover the construction of an SRAM inverter pair stacked vertically or with the SRAM laid out in single plane stacked on top of logic transistors.

At its website Viciciv (Sunnyvale, Calif.) claimed its goal is to create a “new paradigm for ASIC and ASSP design” It also claimed to have an innovative technology to simplify system design with time to market, ease of use, low cost and high performance ASICs. However, no details are provided at the website.

The company also claimed to have validated architectural and technological innovations and be in the process of delivering the company’s first product. The technology would allows “instant” custom designs to be created with “no NRE costs” the company also claimed, which could be consistent with an SRAM-based field programmable gate array (FPGA).

Two patents (numbers 06855988 and 06856030) were issued by the U.S. Patent Office on Feb. 15, 2005 and the rights assigned to Viciciv Technologies Inc. (Sunnyvale, Calif.).

The ‘030’ patent is titled: “Semiconductor latches and SRAM devices” and covers an SRAM cell made using thin-film transistor materials in a three dimensional arrangement. In one embodiment the SRAM could be constructed in a semiconductor thin-film layer located substantially above logic transistors. In this case the SRAM cell would consume no extra silicon area. This embodiment is intended for use in slow access memory and look-up table applications, the abstract said.

Another embodiment comprises a strong inverter and a strong access device constructed on a semiconductor substrate layer with a weak inverter and a weak access device constructed in a semiconductor thin layer located vertically above the strong device. This embodiment would be used for high density and high speed memory applications, the abstract said.

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