WASHINGTON — NEC Corp., in its latest research results reported at the International Electron Devices Meeting here, has announced an enhanced three-terminal Nanobridge switch that will be the basis of a novel form of field programmable gate array (FPGA). The so-called cell-based integrated circuit (CBIC) is expected to be one-tenth the size of the equivalent FPGA.
In research done together with two Japanese government agencies — the National Institute for Materials Science (NIMS) and the Japan Science and Technology Agency (JST) — NEC has enhanced on its two-terminal CBIC announced at the International Solid State Circuits Conference in February 2004. The two-terminal device is composed of a solid electrolyte sandwiched between two terminals. In the three-terminal CBIC a gate has been added to the switch which controls electrochemical reactions (deposition and dissolution) of metallic ions in the solid electrolyte.
With the two-terminal NanoBridge, switching between the on and off states was achieved by applying a voltage across the electrical path between the two terminals, resulting in the flow of a large electric current during switching. A vast amount of power was consumed during switching, with greater chance of device breakdown.
The three-terminal device meets the requirements for programmable-logic applications with its improved controllability, low resistance and reliability, according to Toshitsugu Sakamoto, principal researcher at the Fundamental and Environmental Research Labs. “In the three-terminal NanoBridge switch we were able to reduce current during switching to less than 10 microamps and maintain a switching speed of approximately 0.3 sec. at 0.4 volts and less than 1 msec. at 1.5 volts, and we did not require the use of a pass transistor," said Sakamoto.
NanoBridge technology utilizes the atom switching effect of a nanometer scale metal bridge, in which an electrically conductive channel is created or annihilated by stretching a metallic bridge controlled by an electrochemical reaction inside a solid electrolyte.
For the three-terminal NanoBridge structure the drain size has been decreased to restrict the area in which metal can precipitate out. In addition the distance between the source and drain has been made shorter to prevent shorting to the gate.
A 45-nm switch
On another front, NEC Corp. and NEC Electronics Corp. announced a development of 45-nm technology node by improving the on-off ratio in sub-10-nm planar bulk transistors. The new device technology has been enabled by a new elevated source/drain extension (SDE) structure created via a silicon selective-epitaxial growth technique.
Although silicon devices continue to scale, some observers claim that their operation principles are nearing physical limits. However, in 2003 demonstrated planar bulk transistors with valid functionality at 5-nm gate-length. At that time, other issues would have prevented their implementation but NEC’s SDE work has re-enabled that scaling.
"NEC's newly developed device technology has successfully solved this issue and its potential was shown by actual test-fabrication carried out on 6-nm transistors, proving the potential for continuous and further technological advancement of system-on-silicon until 2020 through highly reliable, low-cost planar bulk technology," said Masao Fukuma, vice president of NEC Electronics Corp. at an IEDM briefing here on Tuesday (Dec.6).
The two NEC entities also reported on their joint research on a 45-nm interconnect technology. NEC researchers have developed a molecular-pore-stacked low-k-film that it is claimed can be easily deposited in the fab process and that reduces the parasitic capacitance of interconnects by 24 percent as compared to that exhibited at 65-nm nodes. This is reportedly the lowest parasitic capacitance between 70nm-spaced lines and is expected to realize a 50 percent reduction of the chip size and more than 20 percent reduction in power consumption that those of 65-nm nodes, according to Fukuma.